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AMD’s Vega Architecture Changes Outlined – Everything You Need to Know

AMD has unveiled the changes in its upcoming graphics architecture, Vega, that make it ideal for graphics and computing operations.

Last month, AMD’s Raja Koduri outlined the fact that data sets for pro graphics applications and computing data are continuing to grow in size. Graphics memory, on the other hand, is restricted to dozens of GB of RAM.

Vega Architecture Changes Outlined

In order to efficiently crunch the ever-growing numbers, Vega’s memory controller – called High-Bandwidth Cache Controller – is designed to help GPU access data sets from the outside of the traditional RAM.

According to AMD, what we now call RAM/VRAM will soon be referred to as high-bandwidth cache or HBC. The HBC on some of the Vega-based GPUs will also consist of a chunk of HBM2 memory. We already know that HBM2 offers double the bandwidth per stack and according to AMD, HBM stacks will continue to grow which will offer increased performance and power-efficiency.

Apart from this, the high-bandwidth cache controller is capable of addressing a pool of memory as large as 512GB. Moreover, the pool can potentially encompass to different memory locations i.e. NAND flash, system memory, etc. To better outline this, AMD showcased a photorealistic representation of a bedroom created from hundreds of GBs of data using a Vega-based GPU.

As reported by TechReport; AMD had an early piece of Vega silicon running in its demo room for press. Running the Argent D’Nur level of DOOM’s arcade mode, the chip managed somewhere between 60 to 70 frames per second at 4K on Ultra Settings. The report also states that upon turning on ‘nightmare’ performance metrics, the maximum frame time of 24.8ms after massive explosions were seen.

In addition to this, it was also observed that the chip had 8GB of memory on board, but its type could not be determined.

It has also been confirmed that Vega’s Next-Generation Compute Units (NCUs) have been revamped to execute more instructions per cycle and run at higher clock speeds. This essentially means that an NCU can complete more operations in a single cycle.

The new architecture also boasts a new programmable geometry engine which is not only capable of doubling the performance per clock, but is also comparatively faster at tasks such as tessellation, rendering, and more. In conclusion, the upcoming Vega architecture not only offers increased clock speeds, faster cache, and memory sub-systems, but also better power efficiency and more compute and geometry IPC.