AMD Talks On AMD GCN Architecture At A High-Level

By   /   Jan 19, 2017
AMD GCN Architecture

AMD during CES shed light on architectural details of AMD Vega, however the data was not enough to know everything about Vega, its efficiency, its comparison to other rival graphics cards and how far the new AMD GCN architecture stands out than older GCN.

The new GCN introduced in Vega changes everything. HBCC, memory structure, clock speeds and more are all possible due to new GCN. Vega in fact is an overhaul of AMD’s architecture since mid-1970.

See also: AMD Vega High Bandwidth Cache Doubles Usable Graphics Memory

First, let’s talk about the high-level obvious chipset changes of Vega architecture. The three components on the left shown in the image below are game changer: Geometry pipeline, Compute engine also called as NCU, Pixel engine. The new Primitive shader is lumped under the heading of new programmable Geometry pipeline. However, the old method of doing this was to have a separate pixel, vertex, and geometry shaders fed by a compute engine (ACE) or geometry command process (GCP).

Furthermore, things are different with new Geometry pipeline. A programmer can do things the old way or can take a new path, primitive shader (PS). The picture below is clear that PS is a separate path from VS and GS, this means two methods for programmers to utilize the undisclosed details.

Moreover, in AMD GCN Architecture, PS is much more programmable than before. Programmers will have the option to opt for new method, PS, for doing work over on old shaders.

Previously, GCN devices had a lot of ACEs but one GCP. Although, AMD has not yet revealed much information on existence of multiple GCNs but, they say Geometry pipeline can launch multiple threads at the same rate as the ACEs launch compute threads. Therefore, this implies existence of multiple GCPs.

Second, next generation compute engine or NCU. One interesting thing to note is AMD is calling NCU as replacement for an ACE, if so, then the listed rate is per unit given in the image below. AMD further claims:

NCU is optimized for higher clock speeds and higher IPC

Third, next generation Pixel Engine or NPE. The main addition to NPE is something AMD calls the Draw Stream Rasterizer. It caches primitives, with its small and smart rasterizer: a newly added cache called the on-chip bin cache.

The idea is to save fetches to off-chip memory to pull in polygons as needed for rasterization. Doing so will reduce the load of unneeded work, avoiding the fetching of a polygon or primitive more than once and making GPU do less work.

More information is required to know further on how a Vega GPU will attain maximum capacity. It is the new AMD GCN Architecture that makes Vega a possibility.

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